RISC-V International Open Source Laboratory

@RIOSLaboratory

The RISC-V International Open Source Laboratory (RIOS Lab) will bring the research effort of RISC-V CPU ecosystems from UC Berkeley to the rest of the world

104

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Language Breakdown

Lines of code distribution across 11 owned repositories

326.9M Total LOC

Verilog

323,691,306 lines

99.0%

N/A

SystemVerilog

833,892 lines

0.3%

N/A

Tcl

690,798 lines

0.2%

N/A

C++

383,863 lines

0.1%

N/A

355,599 lines

0.1%

N/A

Other

989,923 lines

0.3%

N/A

I-Shaped Developer

I-shaped

Specialist — deep expertise in Verilog

Verilog

SystemVerilog

Tcl

C++

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Coding Streak

Contribution activity over the past year

1 day

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Followers 104

Albert Li

@allbilly

willardbruce

@willardbruce11-lab

Sougata Chandra

@Sougata0204

@KryptoKode

Ali Aqdas

@aaqdas

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Top Repositories

OpenRPDK28

Open source process design kit for 28nm open process

82 13

OpenXRAM

sram/rram/mram.. compiler

52 7

Verilog

OpenSTDCell28

Open stadard cell library for open 28nm process

A small RISC-V core written in synthesizable Verilog, with the majority of the Verilog code implementation done using GPT-4, that supports the RV32I unprivileged ISA and parts of the privileged ISA, namely M-mode.

Sail architecture definition language with RGen enhancements

3 0

Standard ML

GreenRio-V2.0

Open source RISC-V CPU

3 1